For an organic EL display panel in an organic EL display device which is mounted such as on a cellular phone, PHS, DVD player and PDA (Personal Digital Assistant), one having 396 (132×3) terminal pins (column pins ) with regard to the number of column lines and 162 terminal pins with regard to the row lines is proposed, and the number of terminal pins with regard to the column and the row tends to increase more than the above number.
As drive circuits for such organic EL display panel, patent applications of the present assignee in which D/As are provided for respective corresponding column pins are known (patent documents 1 and 2). In the patent document 2, the D/As provided for respective corresponding column pins receive display data and a reference current, and D/A convert the display data in corresponding to column pins of the organic EL panel according to the reference current to thereby produce a drive current in the column direction or a base current for the drive current.
Further, with respect to a liquid crystal display panel, the number of the terminal pins for the column lines and the row lines is more than the above number.
Patent Document 1: JP2003-234655A
Patent Document 2: JP2003-308043A
Recent years, the number of the drive pins for an organic EL display device tends to increase due to demand for higher resolution. In a full color QVGA for an organic EL display device now being developed, the number reaches up to 360 pins, 120 pins each for R, G and B which at the present requires three drivers.
Now, for a divided resistor and voltage output type D/A which is built-in in a drive circuit such as for a liquid crystal display panel and an organic EL panel, a switch circuit of E/D MOS in which a depression MOS transistor (D-MOS) and an enhancement MOS transistor (E-MOS) are connected in series is usually used as for a high withstanding voltage application (power source voltage of about 20 V).
In this instance, as shown in FIG. 6, a D/A 10 is constituted by a reference voltage generating circuit 1, a selection circuit 2 and a buffer amplifier (voltage follower) 3.
The reference voltage generating circuit 1 uses a divided resistor circuit in which sixteen resistors R1˜R16 are connected in series, and in the D/A 10, the selection circuit 2 receives divided voltages generated between respective resistors in the divided resistor circuit for the reference voltage generating circuit 1. Then, to the selection circuit 2 display data of four bits D0˜D3 are applied, a transistor group constituted by many switch circuits of E/D-MOSs in the selection circuit 2 is selectively ON/OFF driven, one of the divided voltages is selected and sends out to the buffer amplifier 3, and a D/A converted output voltage V0 is generated at an output terminal 3a of the buffer amplifier 3.
Further, in the drawing, white circles (∘) show E-MOS switch transistors TrE and black circles (●) show D-MOS switch transistors TrD.
Vin is a reference input voltage applied externally to the reference voltage generating circuit 1.
“H” (=High level) or “L” (=Low level) signals of the display data of four bits D0˜D3 inputted to the selection circuit 2 are selectively supplied to gates of these transistors via control signal lines 8a˜8h. 
Further, beneath the gate regions of these transistors to which the control signal lines 8a˜8h are to be connected selectively, a source region and a drain region of the respective transistors are formed with a predetermined interval (see FIG. 7, which will be explained later). 9a˜9d are inverters which are connected respectively to the control signal lines 8a, 8c, 8e and 8g, invert the display data D0˜D3 of four bits and apply the same to the respective gates to which the control signal lines 8a, 8c, 8e and 8g are connected.
The divided resistor type D/A 10 selects one row component of switch transistors TrE and switch transistors TrD arranged in lateral direction with respect to one voltage divided point of a resistor connected to the control signal lines 8a˜8h according to “H” or “L” of display data of four bits D0˜D3, turns ON these transistors at the same time and selects one of voltages at divided voltage points of respective resistors in response to the display data of four bits D0˜D3. The selected voltage at the divided voltage point is applied to (+) input of the buffer amplifier 3. Thereby, D/A conversion is performed and an analog voltage V0 is generated at the output terminal 3a. 
In the selection circuit 2, a range C indicated by a dotted line and surrounded by a laterally long rectangular frame usually constitutes one unit region (cell) which is formed as one circuit element in an IC and a switch transistor group of four E-MOSs and four D-MOSs, eight in total is provided in one unit region (cell) C. In addition, a guard ring is provided for every unit region C to separate the regions, and by arranging these unit regions C in longitudinally or laterally the selection circuit 2 in the D/A is constituted. At both ends of the respective unit regions contact pads 6 for wiring are respectively provided.
FIG. 7 is a diagram for explaining a layout of one unit region (cell) formed by transistors constituting the selection circuit 2 in the D/A.
In FIG. 7, numeral 4 is a source-drain forming region in which sources, drains or both of the respective transistors are formed with a predetermined interval corresponding to respective gate intervals between contact pads at both ends.
Namely, in the enhancement MOS TrE (herein below will be called as E-MOS TrE) and depression MOS TrD (herein below will be called as D-MOS TrD), the source-gate-drain are arranged in this order and a source of an E-MOS TrE and a drain of a subsequent D-MOS TrD are formed as a common region. Alternatively, a drain of an E-MOS TrE and a source of a subsequent D-MOS TrD are formed as a common region.
5e is a gate region of a switch transistor TrE, 5d is a gate region of a switch transistor TrD, and the gate regions 5e and 5d are formed in a narrow rectangular shape over the predetermined interval forming the source-drain region. Since the respective transistors are switch MOSs, the gate length of the respective gate regions is short and in contrast the gate width thereof is formed long.
The source•drain forming region 4 is formed as collectives of source•drain regions provided with the predetermined interval between the contact pads 6 provided at both ends. Numeral 7 is a guard ring in a vertically longer rectangular shape provided in the IC, and inside thereof the contact pads 6 and the respective transistors are formed to constitutes one unit region (cell) C.
Further, square points respectively provided on the contact pads 6, guard ring 7 and the gate regions 5e and 5d are contacts.